dc.contributor.author | COJOCARU, Ion | |
dc.date.accessioned | 2024-01-15T10:07:16Z | |
dc.date.available | 2024-01-15T10:07:16Z | |
dc.date.issued | 2009 | |
dc.identifier.citation | COJOCARU, Ion. Studiu structural al redundanţei circuitului digital al contraexemplului Schneider. In: Microelectronics and Computer Science: proc. 6th International Conference, 1-3 Oct. 2009, Chişinău, Republica Moldova, vol. 1, 2009, pp. 395-398. ISBN 978-9975-45-045-4. ISBN 978-9975-45-122-2 (vol. 1). | en_US |
dc.identifier.isbn | 978-9975-45-045-4 | |
dc.identifier.isbn | 978-9975-45-122-2 | |
dc.identifier.uri | http://repository.utm.md/handle/5014/25839 | |
dc.description.abstract | The structurel method and the spatial-temporal truth table description of the functionality for the DC’s methods were used with the purpose to obtain a logic description of the equivalent successive transformations. In conformity with structurel approach the necessary equivalent modifications are made. As a consequence the redundancy of the 6th logic gate and its connections was detected. It was demonstrated that the 6 ≡ 1 error can’t be detected using DALG-II because the blockage of 2 entrances of the exit gate from the DC. | en_US |
dc.language.iso | ro | en_US |
dc.publisher | Technical University of Moldova | en_US |
dc.relation.ispartof | Proceeding of the 6th International Conference on "Microelectronics and Computer Science", oct.1-3, 2009, Chişinău, Moldova | |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 United States | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ | * |
dc.subject | digital circuits | en_US |
dc.subject | integrated circuits | en_US |
dc.subject | logic conflicts | en_US |
dc.subject | Schneider digital circuits | en_US |
dc.title | Studiu structural al redundanţei circuitului digital al contraexemplului Schneider | en_US |
dc.type | Article | en_US |
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