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Pseudo-ring testing of the FPGA memory using software Nios processor

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dc.contributor.author GRIŢCOV, Serghei
dc.contributor.author SOROCHIN, Gherman
dc.contributor.author SESTACOV, Tatiana
dc.date.accessioned 2019-05-16T09:59:26Z
dc.date.available 2019-05-16T09:59:26Z
dc.date.issued 2018
dc.identifier.citation GRIŢCOV, Serghei, SOROCHIN, Gherman, SESTACOV, Tatiana. Pseudo-ring testing of the FPGA memory using software Nios processor. In: Telecomunicaţii, Electronică şi Informatică: proc. of the 6th intern. conf., May 24-27, 2018. Chişinău, 2018, pp. 328-331. ISBN 978-9975-45-540-4. en_US
dc.identifier.isbn 978-9975-45-540-4
dc.identifier.uri http://repository.utm.md/handle/5014/2479
dc.description.abstract In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization. en_US
dc.language.iso en en_US
dc.publisher Tehnica UTM en_US
dc.rights Attribution-NonCommercial-NoDerivs 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.subject FPGA en_US
dc.subject Field Programmable Gate Array en_US
dc.subject Nios processor en_US
dc.subject C language en_US
dc.subject procesoare Nios en_US
dc.subject limbajul C en_US
dc.title Pseudo-ring testing of the FPGA memory using software Nios processor en_US
dc.type Article en_US


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