Parity analysis of convergent fan-out signals for the Schneider’s counterexample digital circuit

Abstract

The digital circuit, DC, of the counterexample Schneider was used as a logic structure to which it was demonstrated the insufficiently of the sensitization method for one way (DALG-I), for discovering the error 6≡0 and the argument for elaborating DALG-II. In it’s proven that the efficiency of DALG-II was demonstrated for a possible specific error. The results of the testability estimation for this circuit come with a doubt for the correctness of the structure and for the efficiency DALG-II for detecting 6≡1.