Aspects of generating the tests in the DALG-I concept

Abstract

Once with the enhancement of the integrated circuits (IC), the number of tests and the time of creating them was augmenting much, and the detecting errors tests from the combinational circuits (CC) with convergent fan-out (CFO) couldn’t be created in the DALG-I concept of activating the unique path through the circuit. To solve this deadlock there are proposed 2 ways: 1) the projection for testability (PFT) of CC; 2) the elaboration of efficient algorithms to create the tests, which allows a fast easy way to create tests for different structures and the diminuation of number of tests. Because PFT needs long term and complex studies, the second variant was choosed: it was proposed the algorithm DALG-II of creating the tests [2], based on the simultaneous activation of all the paths CFO. The article presents the results of a study of creating the tests based on the principle DALG-I and the causes of the presence of the effects of compensation or masking the errors.