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Studiu analitic al redundanţei CD al contraexemplului Schneider

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dc.contributor.author COJOCARU, Ion
dc.date.accessioned 2024-01-15T08:09:22Z
dc.date.available 2024-01-15T08:09:22Z
dc.date.issued 2009
dc.identifier.citation COJOCARU, Ion. Studiu analitic al redundanţei CD al contraexemplului Schneider. In: Microelectronics and Computer Science: proc. 6th International Conference, 1-3 Oct. 2009, Chişinău, Republica Moldova, vol. 1, 2009, pp. 390-394. ISBN 978-9975-45-045-4. ISBN 978-9975-45-122-2 (vol. 1). en_US
dc.identifier.isbn 978-9975-45-045-4
dc.identifier.isbn 978-9975-45-122-2
dc.identifier.uri http://repository.utm.md/handle/5014/25834
dc.description.abstract The key problem of the digital circuit (DC) testability always was the elaboration of the efficient test generation methods, their importance grew once with the transition to the new generation of integrated circuits. The structural complexity and the enhanced functionality of a DC lead to enamors expenses due to test generation. A lot more obvious became the necessity for elaboration the demands, principles and methods for the design for testability (DFT) – DFT of the DC’s. The theoretic bases for the DC’s testability continued to evolve in the same time with the elaboration of the methodology and concepts of DFT. In 1966, Roth elaborates DALG-I [1]. Schneider [2] brings a counterexample DC, in which the error 6≡0 couldn’t be detected according to the DALG-I, also the test existed. In 1967 the DALG-II [3] algorithm appears which guarantees the generation of the test for detecting the error 6≡0. In [4] it is demonstrated that the 6≡0 error is a specific one. In [5, 6] it is demonstrated the possibility of apparition for an unsolvable logic conflicts, and in [7] – the redundancy of this DC. The present paper confirms the redundancy of the Schneider’s DC. en_US
dc.language.iso ro en_US
dc.publisher Technical University of Moldova en_US
dc.relation.ispartof Proceeding of the 6th International Conference on "Microelectronics and Computer Science", oct.1-3, 2009, Chişinău, Moldova
dc.rights Attribution-NonCommercial-NoDerivs 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.subject digital circuits en_US
dc.subject integrated circuits en_US
dc.subject logic conflicts en_US
dc.subject Schneider digital circuits en_US
dc.title Studiu analitic al redundanţei CD al contraexemplului Schneider en_US
dc.type Article en_US


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