Studiu structural al redundanţei circuitului digital al contraexemplului Schneider

Abstract

The structurel method and the spatial-temporal truth table description of the functionality for the DC’s methods were used with the purpose to obtain a logic description of the equivalent successive transformations. In conformity with structurel approach the necessary equivalent modifications are made. As a consequence the redundancy of the 6th logic gate and its connections was detected. It was demonstrated that the 6 ≡ 1 error can’t be detected using DALG-II because the blockage of 2 entrances of the exit gate from the DC.