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Design and partitioning across 2 strata in 3D IC architectures

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dc.contributor.author PLETEA, Ionica-Marcela
dc.contributor.author SONTEA, Victor
dc.date.accessioned 2024-12-07T16:19:13Z
dc.date.available 2024-12-07T16:19:13Z
dc.date.issued 2024
dc.identifier.citation PLETEA, Ionica-Marcela and Victor SONTEA. Design and partitioning across 2 strata in 3D IC architectures. In: Electronics, Communications and Computing (IC ECCO-2024): The conference program and abstract book: 13th intern. conf., Chişinău, 17-18 Oct. 2024. Technical University of Moldova. Chişinău: Tehnica-UTM, 2024, pp. 107-108. ISBN 978-9975-64-480-8 (PDF). en_US
dc.identifier.isbn 978-9975-64-480-8
dc.identifier.uri http://repository.utm.md/handle/5014/28767
dc.description Only Abstract en_US
dc.description.abstract The 2D tools used for producing integrated circuits can be adapted for de 3D integration taking into consideration the design, technological files and methodology used for implementation. A suitable design for 3D integration using 2D instruments should have about half memory area and half standard cells area, memories going to the 2nd stratum and standard cells remaining on the 1st stratum. Usually these 2 strata will have different placement utilization, but anyhow much smaller than 100% (this is very depended by design size and shape as well as by memories’ size, shape and number). en_US
dc.language.iso en en_US
dc.publisher Technical University of Moldova en_US
dc.relation.ispartofseries Electronics, Communications and Computing (IC ECCO-2024): 13th intern. conf., 17-18 Oct. 2024;
dc.rights Attribution-NonCommercial-NoDerivs 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.subject strata en_US
dc.subject partitioning en_US
dc.subject integration en_US
dc.subject memories en_US
dc.title Design and partitioning across 2 strata in 3D IC architectures en_US
dc.type Article en_US


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  • 2024
    The 13th International Conference on Electronics, Communications and Computing (IC ECCO-2024)

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