dc.contributor.author | MELNIC, Radu | |
dc.contributor.author | BALMUS, Ion | |
dc.contributor.author | ABABII, Victor | |
dc.date.accessioned | 2019-10-22T13:25:17Z | |
dc.date.available | 2019-10-22T13:25:17Z | |
dc.date.issued | 2014 | |
dc.identifier.citation | MELNIC, Radu, BALMUS, Ion, ABABII, Victor et al. Synthesis of Multi-core Architecture for Optimal Control. In: Microelectronics and Computer Science: proc. of the 8th intern. conf., October 22-25, 2014. Chişinău, 2014, pp. 379-381. ISBN 978-9975-45-329-5. | en_US |
dc.identifier.isbn | 978-9975-45-329-5 | |
dc.identifier.uri | http://repository.utm.md/handle/5014/5034 | |
dc.description.abstract | This paper offers a solution to the problem of optimal control system synthesis based on uniform multi-core architecture. For this purpose the equations that describe the control system are decomposed into a set of homogeneous equations with the same complexity and the search for the minimum value of the functional optimization is done as a sequential iterative search using a set of one-dimensional equations. In order to ensure maximum efficiency, computational power of the optimal solutions management, is uniformly distributed on a set of computing architecture controllers. AVR microcontrollers and industrial network standard I2C series were used to study the behavior of the control system. In the design process there where developed: math models, the structure of the control system, data protocol, the behavioral algorithm and the circuit of the control system based on four microcontrollers. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Tehnica UTM | en_US |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 United States | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ | * |
dc.subject | control system | en_US |
dc.subject | multi-controller architecture | en_US |
dc.subject | I2C bus | en_US |
dc.title | Synthesis of Multi-core Architecture for Optimal Control | en_US |
dc.type | Article | en_US |
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