CTS optimization on 3D integration

Abstract

In this article we have implemented and optimized Clock Tree in a design placed 3D and we have analyzed the results and the impact of reducing wire length on the area, power and timing of the built clock tree. Due to decreasing length of the wires, the number of the buffers and the invertors used to create clock tree is decreasing significantly and optimizing CTS using different strategies leads to a performant clock tree in terms of speed and area.