dc.contributor.author | CAŞCAVAL, Petru | |
dc.date.accessioned | 2019-11-12T12:39:35Z | |
dc.date.available | 2019-11-12T12:39:35Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | CAŞCAVAL, Petru. Bist logic design for a reduced model of 3–coupling faults in random–access memories. In: Microelectronics and Computer Science: proc. of the 4th intern. conf., September 15-17, 2005. Chişinău, 2005, vol. 2, pp. 205-209. ISBN 9975-66-038-X. | en_US |
dc.identifier.isbn | 9975-66-038-X | |
dc.identifier.uri | http://repository.utm.md/handle/5014/6710 | |
dc.description.abstract | A logic design for a built-in self-testing implementation of a march test able to cover a reduced model of 3–coupling faults in n 1 random–access memories (RAMs) is discussed. The logic design is focused on the march test MT-R3CF with 30n operations given by Caşcaval, Bennett, and Huţanu in [1]. To reduce the length of the test, only the coupling faults between physically adjacent memory cells have been considered. To compare marh test MT-R3CF with other published tests, simulation results are also presented in this paper. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Technical University of Moldova | en_US |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 United States | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ | * |
dc.subject | RAM testing | en_US |
dc.subject | reduced 3–coupling faults | en_US |
dc.subject | march tests | en_US |
dc.subject | built–in self–testing | en_US |
dc.title | Bist logic design for a reduced model of 3–coupling faults in random–access memories | en_US |
dc.type | Article | en_US |
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