CTS optimization on 3D integration

PLETEA, Ionica-Marcela; SONTEA, Victor; ALECSANDRESCU, Iolanda

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dc.contributor.author	PLETEA, Ionica-Marcela
dc.contributor.author	SONTEA, Victor
dc.contributor.author	ALECSANDRESCU, Iolanda
dc.date.accessioned	2019-10-31T12:22:44Z
dc.date.available	2019-10-31T12:22:44Z
dc.date.issued	2019
dc.identifier.citation	PLETEA, Ionica-Marcela, SONTEA, Victor, ALECSANDRESCU, Iolanda. CTS optimization on 3D integration. In: Electronics, Communications and Computing: extended abstracts of the 10th Intern. Conf.: the 55th anniversary of Technical University of Moldova, Chişinău, October 23-26, 2019. Chişinău, 2019, p.62. ISBN 978-9975-108-84-3.	en_US
dc.identifier.isbn	978-9975-108-84-3
dc.identifier.uri	http://repository.utm.md/handle/5014/5776
dc.description.abstract	In this article we have implemented and optimized Clock Tree in a design placed 3D and we have analyzed the results and the impact of reducing wire length on the area, power and timing of the built clock tree. Due to decreasing length of the wires, the number of the buffers and the invertors used to create clock tree is decreasing significantly and optimizing CTS using different strategies leads to a performant clock tree in terms of speed and area.	en_US
dc.language.iso	en	en_US
dc.publisher	Tehnica UTM	en_US
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 United States	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.subject	3D integration	en_US
dc.subject	area reduction	en_US
dc.subject	congestion	en_US
dc.subject	CTS optimization	en_US
dc.title	CTS optimization on 3D integration	en_US
dc.type	Article	en_US