Hardware implementation of Hopfield-like neural networks: Quantitative analysis of FPGA approach

ZAPOROJAN, Sergiu; CARBUNE, Viorel; SLAVESCU, Radu Razvan

dc.contributor.author	ZAPOROJAN, Sergiu
dc.contributor.author	CARBUNE, Viorel
dc.contributor.author	SLAVESCU, Radu Razvan
dc.date.accessioned	2022-04-26T06:08:11Z
dc.date.available	2022-04-26T06:08:11Z
dc.date.issued	2021
dc.identifier.citation	ZAPOROJAN, Sergiu, CARBUNE, Viorel, SLAVESCU, Radu Razvan. Hardware implementation of Hopfield-like neural networks: Quantitative analysis of FPGA approach. In: 17th International Conference on Intelligent Computer Communication and Processing: proc. IEEE ICCP., 28-30 Oct. 2021. 2021, Cluj-Napoca, Romania, 2021, pp. 243-250. ISBN 978-1-6654-0976-6.	en_US
dc.identifier.isbn	978-1-6654-0976-6
dc.identifier.uri	https://doi.org/10.1109/ICCP53602.2021.9733628
dc.identifier.uri	http://repository.utm.md/handle/5014/20217
dc.description	Acces full text - https://doi.org/10.1109/ICCP53602.2021.9733628	en_US
dc.description.abstract	This paper provides a rigorous analysis of FPGA implementation of Hopfield-like neural networks. The relationship between the hardware resources used to synthesize the data path and those used to provide network connections is discussed, as well as the distribution of these resources and how it depends on the variation in the architectural parameters of the network. The analysis presented in this paper is based on Intel/Altera Cyclone FPGA devices.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 United States	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.subject	machine learning	en_US
dc.subject	Hopfield neural networks	en_US
dc.subject	neural networks	en_US
dc.subject	analytical models	en_US
dc.subject	hardware	en_US
dc.subject	embedded intelligence	en_US
dc.title	Hardware implementation of Hopfield-like neural networks: Quantitative analysis of FPGA approach	en_US
dc.type	Article	en_US